Accelerator for a read-channel design and simulation tool

Abstract

A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses a coset operating mode and nonzero-syndrome-based decoding to accelerate the simulation of the read-channel’s error-rate characteristics corresponding to different parity-check matrices employed in the read-channel’s turbo-decoder, such as a low-density parity-check decoder. The acceleration is achieved through recycling some previously generated log-likelihood-ratio values, which enables the method to sometimes bypass certain time-consuming processing steps therein.

Aleksandr Petiushko Александр Петюшко
Aleksandr Petiushko Александр Петюшко
Director, Head of ML Research / Adjunct Professor / PhD

Principal R&D Researcher (15+ years of experience), R&D Technical Leader (10+ years of experience), and R&D Manager (8+ years of experience). Running and managing industrial research and academic collaboration (35+ publications, 30+ patents). Inspired by theoretical computer science and how it changes the world.